1. Field of the Invention
The present invention relates to a driver, and more particularly, to a low power, high speed driving circuit with auto-calibration functionality.
2. Description of the Prior Art
As the resolution of image sensors or display increases, the data rate of becomes very high. As a result, a requirement for a high speed driver with superior performance grows. Among all kinds of high speed drivers, a low voltage differential signal (LVDS) technique is frequently utilized due to a lower electromagnetic interference (EMI), a lower power consumption and a better signal integrity than those of a conventional CMOS full swing driver. Please refer to FIG. 1, which is a diagram of a conventional LVDS driver for driving a pair of loads R1 and R2. The conventional LVDS driver 100 is composed of two PMOS transistors M1, M2, two NMOS transistors M3, M4, and two constant current sources I1 and I2 connected to a reference supply voltage VDD and a reference ground GND, respectively, wherein each current source I1, I2 has a constant current I flowing through. The transistors M2 and M4 are connected to a first input voltage VIP of a differential signal pair through their gates and transistors M1 and M3 are connected to a second input voltage VIN of the differential signal pair through their gates. When the first input voltage VIP is high (which implies that the second input voltage VIN is low), the transistors M1 and M4 are switched on and the current I flows through the reference supply voltage VDD, the current source I1, the transistor M1, the loads R1 and R2, the transistor M4, the current source I2 and finally to the reference ground GND. Assuming a 1.25V common mode voltage is sustained at output node OP and the output node ON, and the loads R1 and R2 are both equivalently 50 ohms, the biasing current I can be derived as 2 mA for a typical output swing of ±0.2V at the output node OP and the output node ON.
As the data rate rises up to giga bits per second (Gbps) and cable length becomes longer, the impedance matching issue becomes crucial to prevent signal reflection at both the transmitter side and the receiver side. For the LVDS driver 100 shown in FIG. 1, the impedance matching means that the impedance towards each side of the output node OP (or the output node ON) should be conjugate with each other. Since the load R1 driven by a signal traveling from the output node ON through a cable has a resistance of 50 ohms as well as a characteristic impedance of the cable, the impedance towards the opposite side against the load R1 should also be 50 ohms to match the load R1. However, for the LVDS driver 100 in FIG. 1, when the first input voltage VIP is high, the impedance towards the opposite side against the load R1 is almost infinite (the connection to the transistor M3 is open circuited and the connection to the transistor M1 and the current source I, is also open circuited), and therefore the required matching is out of the question. Please refer to FIG. 2, which is a diagram of a conventional LVDS driver 200 with matching resistors R3 and R4 implemented therein. The conventional LVDS driver 200 is composed of two PMOS transistors M1, M2, two NMOS transistors M3, M4, and two constant current sources I1′ and I2′ connected to a reference supply voltage VDD and a reference ground GND, respectively, wherein each current source I1′, I2′ has a constant current 2*I flowing through. The matching resistors R3 and R4 are both designed as 50 ohms to match loads R1 and R2, respectively. For the LDVS driver 200 in FIG. 2, the impedance towards the opposite side against the load R1 is the matching resistor R3 and therefore a proper matching can be achieved. Nevertheless, this modified LVDS driver 200 accomplishes the proper matching at the expense of extra current flowing through the matching resistors R3 and R4, doubling the overall power consumption.
For some applications, the applied driver has to further fulfill some other specification requirements: for example, the Mobile Industry Processor Interface (MIPI) standard demands a very low supply voltage of 0.4V, and a common mode voltage of 0.2V while maintaining an output swing of ±0.1V. In this case, a tail current source connecting reference ground is impossible to be applied. Please refer to FIG. 3, which is a diagram of a conventional LVDS driver 300 for MIPI standard. The conventional LVDS driver 300 is composed of two PMOS transistors M1′, M2′, two resistors R3, R4 connected to a reference ground GND, and a constant current source I3′″ connected to a reference supply voltage VDD, wherein the current source I3′″ has a constant current 4*I′ flowing through. When the first input voltage VIP is high, the current from the current source I3′″ travels through the transistor M1 and then splits into two, one quarter of the current keeps driving the loads R1′ and R2′ and then travels toward the reference ground GND through the resistor R4′; while the remaining current is conducted to the reference ground GND through the resistor R3′. To fulfill the specification requirements of the MIPI standard, the current 4*I′ sourced from the current source I3′″ is equal to 8 mA, and each of the resistors R1′, R2′, R3′ and R4′ is 50 ohms to achieve proper matching. The LDVS driver 300 shown in FIG. 3 can successively meet the requirements of the MIPI standard but still suffers from an over-large power consumption (8 mA for one single driver).